1. Field of the Invention
The present invention relates to a variable delay circuit which controls a delay circuit provided on a transfer path to vary the delay time of the delay circuit and to a semiconductor integrated circuit device having such a delay circuit.
The circuit design mainstream utilizes clock synchronization due to the recent progress towards increasing of the operation speed and the integration density. Hence, it becomes important to suitably supply a given circuit with a clock that is synchronized with an external clock signal. The latest art uses a DLL (Delay Locked Loop) circuit having the minimum delay time unit equal to approximately 200 ps in order to generate an internal clock which is synchronism with the external clock. As the frequency of the internal clock is increased, it is required that a variable delay circuit using the DLL circuit has a higher precision.
2. The Description of the Related Art
A description will now be given, with reference to FIG. 1, of a conventional variable delay circuit.
The circuit shown in FIG. 1 has a four-stage delay circuit consisting of first, second, third and fourth delay circuits 201, 202, 203 and 204, respectively.
The first delay circuit 201 includes gates G201 and G202, and the second delay circuit 202 includes gates G203, G204 and G205. The third delay circuit 203 includes gates G206, G207 and G208, and the fourth delay circuit 204 includes gates G209, G210 and G211. The first through fourth delay circuits 201 through 204 are supplied with switch input signals via switch terminals (SW) P203 through P206. One of the switch input signals is switched to a high level (H), an input clock signal applied to an input terminal P201 is delayed by a delay time based on which one of the switch input signals is switched to the high level. A resultant delayed clock signal is output via an output terminal P202. Each of the gates G201-G211 has a unit delay time 1 td.
In the operation of the first delay circuit 201, the gate G201 is masked when the signal applied to the switch terminal P203 is at a low level (L). The output signal obtained at the output terminal 202 is always at the low level irrespective of whether the other input of the gate G201 is high or low. The gate 201 is released from the masked state when the signal applied to the switch terminal P203 is at the high level. If the potential of the other input of the gate G201 successively changes to the high level and the low level in this order, the output signal of the output terminal P202 is changed to the high level and the low level in this order. Hence, when the signal applied to the switch terminal P203 is at the high level, the delay time from the input terminal P201 to the output terminal P202 is equal to 2 td because the input signal passes through the two stages of gates therebetween.
In the operation of the second delay circuit 202, the gate G203 is masked when the signal applied to the switch terminal P204 is at the low level. The output signal of the output terminal P202 is always at the low level irrespective of whether the other input of the gate G203 is high or low. The gate 203 is released from the masked state when the signal applied to the switch terminal P204 is at the high level. If the potential of the other input of the gate G203 successively changes to the high level and the low level in this order, the output signal of the output terminal P202 is changed to the high level and the low level in this order. Hence, when the signal applied to the switch terminal P204 is at the high level, the delay time from the input terminal P201 to the output terminal P202 is equal to 4 td because the input signal passes through the four stages of gates therebetween.
Similarly, the output signal of the output terminal P202 obtained when the third delay circuit 203 or the fourth delay circuit 204 is activated by the switch signal applied to the switch terminal P205 or P206, respectively. If the switch signal applied to the switch terminal P205 is at the high level, the delay time provided from the input terminal P201 to the output terminal P202 is equal to 6 td, which corresponds to 6 gates. When the switch signal applied to the switch terminal P206 is at the high level, the delay time from the input terminal P201 to the output terminal P202 is equal to 8 td, which corresponds to 8 gates.
Hence, the conventional variable delay circuit having four stages of delay circuits is capable of providing the variable times equal to 2 td to 8 td.
A description will now be given, with reference to FIG. 2, of a conventional DLL circuit utilizing the above-mentioned conventional variable delay circuit.
Referring to FIG. 2, a conventional DLL circuit 210 includes a variable delay circuit 212, a phase comparator circuit 215, and a delay control circuit 216. The variable delay circuit 212 delays an external clock signal received by an input circuit 211 by a given delay time, and outputs the delayed external clock signal to an output circuit 213. The phase comparator circuit 215 compares the phase of a reference signal xe2x80x9crefxe2x80x9d supplied from the input circuit 211 with the phase of a signal xe2x80x9cinxe2x80x9d output by a dummy circuit 214. The signal output by the dummy circuit 214 has a delay time equal to the sum of the delay times of the input circuit 211, the variable delay circuit 212 and the output circuit 213 and the delay times of wiring lines provided between the input circuit 211 and the output circuit 213. The conventional DLL circuit 210 thus configured functions to delay the clock signal from the input circuit 211 with a precision of approximately 200 ps so that the output clock signal having a predetermined phase relationship with the clock signal from the input circuit 211.
A description will now be given, with reference to FIG. 3, of a phase setting process of the DLL circuit 210. In FIG. 3, a symbol xe2x80x9crefxe2x80x9d denotes the reference signal output by the input circuit 211, and a symbol xe2x80x9cinxe2x80x9d denotes the signal output by the dummy circuit 214. The DLL circuit 210 delays the external clock received via the input circuit 211 by a given delay time through the variable delay circuit 212. The output circuit 213 receives the delayed clock signal from the variable delay circuit 212 and supplies a circuit of the following stage with the clock signal which has been pulled in phase with the external clock signal.
The dummy circuit 214 supplies the phase comparator circuit 215 with the signal xe2x80x9cinxe2x80x9d having the same delay time as that equal to the sum of the delay times of the input circuit 211, the variable delay circuit 212 and the output circuit 213 and the delay times of the wiring lines provided therebetween (step S101). The input circuit 211 outputs, as the reference signal xe2x80x9crefxe2x80x9d, the external clock signal to the phase comparator circuit 215 (step S101). The phase comparator circuit 215 determines whether the signals xe2x80x9crefxe2x80x9d and xe2x80x9cinxe2x80x9d are in phase (step S102). If the signals xe2x80x9crefxe2x80x9d and xe2x80x9cinxe2x80x9d are out of phase, the relative phase relationship therebetween is determined (step S102).
If the signals xe2x80x9crefxe2x80x9d and xe2x80x9cinxe2x80x9d are in phase (xe2x80x9cjustxe2x80x9d at step S102), the delay control circuit 216 holds the current delay time of the variable delay circuit 212, and the phase comparator circuit 215 periodically performs the phase comparing operation.
If it is discerned, at step S102, that the signal xe2x80x9crefxe2x80x9d from the input circuit 211 lags behind the signal xe2x80x9cinxe2x80x9d (xe2x80x9cxe2x88x921xe2x80x9d at step S102), the phase comparator circuit 215 detects the phase difference therebetween. The delay control circuit 216 controls, based on the detected phase difference, the variable delay circuit 212 to reduce the delay time one stage by one stage (step S103). Then, the process returns to step S101 so that the steps S101 and S102 via step S103 are repeatedly carried out at predetermined intervals.
If it is discerned, at step S102, that the signal xe2x80x9cinxe2x80x9d from the dummy circuit 214 lags behind the signal xe2x80x9crefxe2x80x9d (xe2x80x9c+1xe2x80x9d of step S102), the phase comparator circuit 215 detects the phase difference therebetween. The delay control circuit 216 controls, based on the detected phase difference, the variable delay circuit 212 to increase the delay time one stage by one stage (step S104). Then, the process returns to step S101 so that the steps S101 and S102 via step S104 are repeatedly carried out at predetermined intervals.
However, the conventional variable delay circuits as shown in FIG. 1 have a disadvantage in which a delay time shorter than the unit delay time 2 td, for example, a delay time 1 td cannot be obtained and the precision is restricted to 2 td.
It is a general object of the present invention to provide a variable delay circuit in which the above disadvantage is eliminated.
A more specific object of the present invention is to provide a variable delay circuit which has a shorter delay time and a capability of controlling the delay time with a higher precision.
The above objects of the present invention are achieved by a variable delay circuit comprising: a load on a signal transfer line, at least one transistor connected in parallel with the signal transfer line, wherein a gate capacitance of each of the above at least one transistor being controlled by a gate voltage thereof so that a signal on the signal transfer line is delayed in response to a magnitude of the gate capacitance connected thereto. A fine control of the gate capacitance can be realized by the gate voltage. Hence, the delay time by which the input signal is delayed can finely be varied.
The variable delay circuit may be configured so that there is provided, in the signal transfer line, a plurality of transistors connected in parallel, and the plurality of transistors provide delay times varied in arithmetical series. Hence, the input signal can be delayed by the delay time which is varied in arithmetical series.
The variable delay circuit may be configured so that there is provided, in the signal transfer line, a plurality of transistors connected in parallel, and the plurality of transistors provide delay times varied in geometrical series. Hence, the input signal can be delayed by the delay time which is varied in geometrical series.
The above objects of the present invention are also achieved by a variable delay circuit comprising: a delay circuit functioning as a load on a signal transfer line, the delay circuit being connected in parallel with the signal transfer line and comprised of a plurality of transistors connected in series, a gate capacitance of at least one of the plurality of transistor being controlled by a gate voltage thereof so that a signal on the signal transfer line can be delayed by a delay time varied based on the gate capacitance. A fine control of the gate capacitance can be realized by the gate voltage. Hence, the delay time by which the input signal is delayed can finely be varied.
The above objects of the present invention are also achieved by a variable delay circuit comprising: a plurality of delay circuits connected in parallel with a signal transfer line, each of the delay circuits functioning as a load on the signal transfer line, each of the delay circuits comprising a respective capacitor having a different capacitance, one of the delay circuits being connected so that the capacitor of the above one of the delay circuits is connected in parallel with the signal transfer line. Thus, the delay time can be varied by determining the delay circuit to be selected.
The above objects of the present invention are also achieved by a semiconductor integrated circuit device comprising: a first variable delay circuit having delay circuits each capable of delaying an input signal, the first variable delay circuit having a plurality of stages of delay circuits; a second variable delay circuit each having a signal delay function having a precision higher than that of the first variable delay circuit, the second variable delay circuit having a plurality of stages of delay circuits; first and second phase comparator circuits respectively performing comparing operations on an input clock signal and an output clock signal with respective precisions of the first and second variable delay circuits; first and second delay control circuits respectively controlling delay times of the first and second variable delay circuits on the basis of results of the phase comparing operations; and a number-of-stages setting circuit determining a number of stages of the second variable delay circuit on the basis of a first delay time obtained when the input clock signal passes through n stages of the second variable delay circuit and a second delay time obtained when the input clock signal passes through n+1 stages thereof.
The semiconductor integrated circuit device may be configured so that the number-of-stages setting circuit determines the number of stages so that a delay time equal to one stage of the first variable delay circuit is equal to or greater than the first delay time but equal to or less than the second delay time.
The semiconductor integrated circuit device may be configured so that the first and second variable delay circuits are connected in this order or vice versa.
The semiconductor integrated circuit device may be configured so that: the first and second delay control circuits control the first and second variable delay circuits to increase the number of stages of the first variable delay circuit by one and decrease the delay time of the second variable delay circuit in a case where there is a need to provide a delay time exceeding a maximum delay time of the second variable delay circuit; and the first and second delay control circuits control the first and second variable delay circuits to decrease the number of stages of the first variable delay circuit by one and increase the delay time of the second variable delay circuit in a case where there is a need to provide a delay time less than a minimum delay time of the second variable delay circuit.
The semiconductor integrated circuit device may be configured so that the delay time of one stage of the first variable delay circuit is adjusted by an external command.
The semiconductor integrated circuit device may be configured so that a time equal to the precision of the first phase comparator circuit is longer than the delay time of one stage of the first variable delay circuit.
The semiconductor integrated circuit device may be configured so that the first phase comparator circuit has a reference for varying the delay time, the reference being located within a range equal to one stage of the first variable delay circuit, the period starting from a rising edge of one of the input and output clock signals.
The semiconductor integrated circuit device may be configured so that the second phase comparator circuit has a reference for varying the delay time, the reference being located within a range equal to one stage of the second variable delay circuit, the period starting from a rising edge of one of the input and output clock signals.
The semiconductor integrated circuit device may be configured so as to further comprise a timing generating circuit which defines a timing for the phase comparing operations of the first and second phase comparator circuits.
The semiconductor integrated circuit device may further comprise first and second shift signal generating circuits which generate first and second shift signals which instruct the first and second delay control circuits to vary the delay times of the first and second variable delay circuits on the basis of results of the phase comparing operations by the first and second phase comparator circuits.
The semiconductor integrated circuit device may be configured so that the first and second shift signal generating circuits instruct the first and second delay control circuits to vary the delay times at respective timings.
The semiconductor integrated circuit device may further comprise a frequency dividing circuit which frequency-divides an external clock signal so that a reference signal used in the phase comparing operations by the first and second phase comparator circuits can be generated.
The semiconductor integrated circuit device may be configured so that the frequency dividing circuit has a frequency dividing ratio which is increased when the results of the phase comparing operations of the first and second phase comparator circuits show that there is no need to vary the delay times of the first and second variable delay circuits and which is decreased when the result of the phase comparing operation of the first phase comparator circuit shows that there is a need to vary the delay time of the first variable delay circuit.
The semiconductor integrated circuit device may be configured so that the frequency dividing circuit has a frequency dividing ratio which is decreased when the result of the phase comparing operation of the second phase comparator circuit shows there is a need to vary the delay time of the second variable delay circuit and change the number of stages thereof in an identical direction a plurality of number of times.
The semiconductor integrated circuit device may be configured so that the plurality of number of times is set by an external command.
The semiconductor integrated circuit device may be configured so that it further comprises: a frequency dividing circuit which frequency-divides an external clock signal; and a third phase comparator circuit comparing the external clock signal with a clock signal from the first or second variable delay circuit and instructing the frequency dividing circuit to successively change a frequency dividing ratio on the basis of a result of a phase comparing operation of the third phase comparator circuit.
The semiconductor integrated circuit device may be configured so that the third phase comparator circuit instructs the frequency dividing circuit to increase the frequency dividing ratio when the third phase comparator circuit judges that there is no need to vary the delay times of the first and second variable delay circuits.
The semiconductor integrated circuit device may be configured so that the third phase comparator circuit instructs the frequency dividing circuit to decrease the frequency dividing ratio when the third phase comparator circuit judges that there is a need to vary the delay times of the first and second variable delay circuits.
The semiconductor integrated circuit device may be configured so that the third phase comparator circuit instructs the frequency dividing circuit to decrease the frequency dividing ratio when the third phase comparator circuit judges that there is a need to vary the delay times of the first and second variable delay circuits and successively change the number of stages thereof in an identical direction a plurality of number of times.
The semiconductor integrated circuit device may be configured so that the plurality of number of times is set by an external command.
The semiconductor integrated circuit device may be configured so that the frequency dividing circuit has a frequency dividing ratio which is decreased at the time of power on.
The semiconductor integrated circuit device may be configured so that the first variable delay circuit has a predetermined delay time at the time of power on.
The semiconductor integrated circuit device may be configured so that the second phase comparator circuit stops operating while the number of stages of the first variable delay circuit is being adjusted on the basis of the result of the phase comparing operation of the first phase comparing circuit.
The semiconductor integrated circuit device may further comprise an input circuit outputting an internal clock signal synchronized with an external clock signal, the internal clock signal being applied to an internal circuit of the semiconductor integrated circuit device.
The semiconductor integrated circuit device may further comprise a low-pass filter via which electricity is supplied to the internal circuit.
The semiconductor integrated circuit device may further comprise a power supply voltage generating circuit which steps down an external power supply voltage, a resultant step-down voltage being applied to a DLL circuit having the first and second variable delay circuits, the first and second phase comparing circuits, the first and second delay control circuits and the number-of-stages setting circuit.
The semiconductor integrated circuit device may further comprise a low-pass filter via which the DLL circuit is grounded.
The semiconductor integrated circuit device may further comprise a capacitor connected in parallel with the DLL circuit.
The semiconductor integrated circuit device may further comprise a pad for making an external connection to the low-pass filter, so that the low-pass filter is grounded via the pad.
The semiconductor integrated circuit device may further comprise a pad specifically used to supply external electricity to the power supply voltage generating circuit.
The semiconductor integrated circuit device may further comprise a first pad specifically provided for grounding the power supply voltage generating circuit and a second pad specifically provided for grounding the low-pass filter.